Advanced Integrated Circuit Process LLC v. United Microelectronics Corporation

Page 1 of 39
IN THE UNITED STATES DISTRICT COURT
FOR THE EASTERN DISTRICT OF TEXAS
MARSHALL DIVISION
ADVANCED INTEGRATED CIRCUIT
PROCESS LLC,
Plaintiff,
v.
UNITED MICROELECTRONICS
CORPORATION,
Defendant.
§
§
§
§
§
§
§
§
§
§
§
§
§
Case No. 2:24-CV-730-JRG
(Lead Case)
ADVANCED INTEGRATED CIRCUIT
PROCESS LLC,
Plaintiff,
v.
TAIWAN SEMICONDUCTOR
MANUFACTURING COMPANY
LIMITED,
Defendant.
§
§
§
§
§
§
§
§
§
§
§
§
§
Case No. 2:24-CV-623-JRG
(Member Case)
MEMORANDUM OPINION AND ORDER
On December 18, 2025, the Court held a hearing to determine the proper construction of
the disputed claim terms in U.S. Patent No. 7,579,227 (“’227 Patent”), U.S. Patent No. 7,923,764
(“’764 Patent”), U.S. Patent No. 8,253,180 (“’180 Patent”), U.S. Patent No. 8,587,076 (“’076
Patent”), and U.S. Patent No. 8,796,779 (“’779 Patent”) (collectively, the “Asserted Patents”).
Having reviewed the arguments made by the parties at the hearing and in their claim construction
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 1 of 39 PageID #:
<pageID>

Page 2 of 39
briefing (Dkt. Nos. 159, 162, 164)1, having considered the intrinsic evidence, and having made
subsidiary factual findings about the extrinsic evidence, the Court hereby issues this Claim
Construction Memorandum and Order. See Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir.
2005) (en banc); see also Teva Pharm. USA, Inc. v. Sandoz, Inc., 135 S. Ct. 831, 841 (2015).
1 Citations to the parties’ filings are to the filing’s number in the docket (Dkt. No.) and pin cites
are to the page numbers assigned through ECF.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 2 of 39 PageID #:
<pageID>

Page 3 of 39
TABLE OF CONTENTS
I. 	BACKGROUND ................................................................................................................ 4
II. 	APPLICABLE LAW .......................................................................................................... 5
III. 	LEVEL OF ORDINARY SKILL IN THE ART .............................................................. 10
IV. 	CONSTRUCTION OF AGREED TERMS ...................................................................... 11
V. 	CONSTRUCTION OF DISPUTED TERMS ................................................................... 12
A. “gate insulating film” ................................................................................................... 12
B. “outer end of the insulating sidewall” .......................................................................... 21
C. “offset sidewall” ........................................................................................................... 24
D. “sidewall spacer”.......................................................................................................... 27
E. “[first] insulating spacers interposed between the [first] gate electrode and the [first]
sidewall spacers” ............................................................................................................... 34
F. “effective work function” ............................................................................................. 36
VI. 	CONCLUSION ................................................................................................................. 38
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 3 of 39 PageID #:
<pageID>

Page 4 of 39
I. 	BACKGROUND
Plaintiff Advanced Integrated Circuit Process LLC (“AICP” or “Plaintiff”) alleges that
Defendant Taiwan Semiconductor Manufacturing Company Limited (“TSMC”) and Defendant
United Microelectronics Corp. (“UMC”) (collectively “Defendants”) infringe the Asserted
Patents. The ’227, ’764, ’180, and ’076 Patents (collectively, the “Hirase Patents”) are in the same
family and share a common specification. The Hirase Patents are generally directed to a
semiconductor device in which a high dielectric constant gate insulating film is formed on an
active region in a substrate, a gate electrode is formed on this gate insulating film, and one or more
sidewalls is formed adjacent to the gate electrode. ’076 Patent at Abstract. “The high dielectric
constant gate insulating film is continuously formed so as to extend from under the gate electrode
to under the insulating sidewall.” Id.
The Abstract of the ’076 Patent states:
A semiconductor device includes: a high dielectric constant gate
insulating film formed on an active region in a substrate; a gate
electrode formed on the high dielectric constant gate insulating film;
and an insulating sidewall formed on each side surface of the gate
electrode. The high dielectric constant gate insulating film is
continuously formed so as to extend from under the gate electrode
to under the insulating sidewall. At least part of the high dielectric
constant gate insulating film located under the insulating sidewall
has a smaller thickness than a thickness of part of the high dielectric
constant gate insulating film located under the gate electrode.
Claim 1 of the ’076 Patent is an illustrative claim and recites the following elements
(disputed terms in italic):
1.A semiconductor device comprising:
a gate insulating film formed on an active region in a substrate and
including Hf;
a gate electrode formed on the gate insulating film;
a insulating sidewall formed on each side surface of the gate
electrode; and
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 4 of 39 PageID #:
<pageID>

Page 5 of 39
wherein a width of the gate insulating film along a gate length is
larger than a width of the gate electrode along the gate length,
and
an end of the gate insulating film under the insulating sidewall is
retracted from an outer end of the insulating sidewall toward
the gate electrode.
The ’779 Patent relates to “metal insulator semiconductor” (MIS) devices “on an identical
substrate.” ’779 Patent at 1:48–51. The ’779 Patent sought to “enable formation of a plurality of
transistors of the same conductivity type having different work functions in a semiconductor
device having a MIS structure in which a high-k film is used as a gate insulating film.” Id. at 3:50–
54. The first transistor’s interface layer is thicker than the second transistor’s interface layer. Id. at
9:55–10:5. The specification states that increasing the thickness of a transistor’s interface layer
leads to an increased “equivalent oxide thickness” (abbreviated by the Patent as “EOT”), which
then results in an increased “effective work function of the transistors.” Id. at 12:47–54.
The Abstract of the ’779 Patent states:
A first MIS transistor and a second MIS transistor of the same
conductivity 	type 	are 	formed 	on 	an 	identical 	semiconductor
substrate. An interface layer included in a gate insulating film of the
first MIS transistor has a thickness larger than that of an interface
layer included in a gate insulating film of the second MIS transistor.
Claim 2 of the ’779 Patent is an illustrative claim and recites the following elements
(disputed terms in italic):
2. The semiconductor device of claim 1, wherein
the first gate electrode includes first sidewall spacers formed on side
surfaces 	thereof 	and 	first 	insulating 	spacers 	interposed
between the first gate electrode and the first sidewall spacers,
the second gate electrode includes second sidewall spacers formed
on 	side 	surfaces 	thereof 	and 	second 	insulating 	spacers
interposed between the second gate electrode and the second
sidewall spacers, and
the first insulating spacers are thinner than the second insulating
spacers.
II. 	APPLICABLE LAW
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 5 of 39 PageID #:
<pageID>

Page 6 of 39
A. Claim Construction
“It is a ‘bedrock principle’ of patent law that ‘the claims of a patent define the invention to
which the patentee is entitled the right to exclude.’” Phillips v. AWH Corp., 415 F.3d 1303, 1312
(Fed. Cir. 2005) (en banc) (quoting Innova/Pure Water Inc. v. Safari Water Filtration Sys., Inc.,
381 F.3d 1111, 1115 (Fed. Cir. 2004)). To determine the meaning of the claims, courts start by
considering the intrinsic evidence. Id. at 1313; C.R. Bard, Inc. v. U.S. Surgical Corp., 388 F.3d
858, 861 (Fed. Cir. 2004); Bell Atl. Network Servs., Inc. v. Covad Commc’ns Grp., Inc., 262 F.3d
1258, 1267 (Fed. Cir. 2001). The intrinsic evidence includes the claims themselves, the
specification, and the prosecution history. Phillips, 415 F.3d at 1314; C.R. Bard, Inc., 388 F.3d at
861. The general rule—subject to certain specific exceptions discussed infra—is that each claim
term is construed according to its ordinary and accustomed meaning as understood by one of
ordinary skill in the art at the time of the invention in the context of the patent. Phillips, 415 F.3d
at 1312–13; Alloc, Inc. v. Int’l Trade Comm’n, 342 F.3d 1361, 1368 (Fed. Cir. 2003); Azure
Networks, LLC v. CSR PLC, 771 F.3d 1336, 1347 (Fed. Cir. 2014) (quotation marks omitted)
(“There is a heavy presumption that claim terms carry their accustomed meaning in the relevant
community at the relevant time.”) cert. granted, judgment vacated, 135 S. Ct. 1846 (2015).
“The claim construction inquiry . . . begins and ends in all cases with the actual words of
the claim.” Renishaw PLC v. Marposs Societa’ per Azioni, 158 F.3d 1243, 1248 (Fed. Cir. 1998).
“[I]n all aspects of claim construction, ‘the name of the game is the claim.’” Apple Inc. v. Motorola,
Inc., 757 F.3d 1286, 1298 (Fed. Cir. 2014) (quoting In re Hiniker Co., 150 F.3d 1362, 1369 (Fed.
Cir. 1998)) overruled on other grounds by Williamson v. Citrix Online, LLC, 792 F.3d 1339 (Fed.
Cir. 2015). First, a term’s context in the asserted claim can be instructive. Phillips, 415 F.3d at
1314. Other asserted or unasserted claims can also aid in determining the claim’s meaning, because
claim terms are typically used consistently throughout the patent. Id. Differences among the claim
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 6 of 39 PageID #:
<pageID>

Page 7 of 39
terms can also assist in understanding a term’s meaning. Id. For example, when a dependent claim
adds a limitation to an independent claim, it is presumed that the independent claim does not
include the limitation. Id. at 1314–15.
“[C]laims ‘must be read in view of the specification, of which they are a part.’” Id. (quoting
Markman v. Westview Instruments, Inc., 52 F.3d 967, 979 (Fed. Cir. 1995) (en banc)). “[T]he
specification ‘is always highly relevant to the claim construction analysis. Usually, it is dispositive;
it is the single best guide to the meaning of a disputed term.’” Id. (quoting Vitronics Corp. v.
Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)); Teleflex, Inc. v. Ficosa N. Am. Corp.,
299 F.3d 1313, 1325 (Fed. Cir. 2002). This is true because a patentee may define his own terms,
give a claim term a different meaning than the term would otherwise possess, or disclaim or
disavow the claim scope. Phillips, 415 F.3d at 1316. In these situations, the inventor’s
lexicography governs. Id.
The specification may also resolve ambiguous claim terms “where the ordinary and
accustomed meaning of the words used in the claims lack sufficient clarity to permit the scope of
the claim to be ascertained from the words alone.” Teleflex, Inc., 299 F.3d at 1325. But,
“‘[a]lthough the specification may aid the court in interpreting the meaning of disputed claim
language, particular embodiments and examples appearing in the specification will not generally
be read into the claims.’” Comark Commc’ns, Inc. v. Harris Corp., 156 F.3d 1182, 1187 (Fed. Cir.
1998) (quoting Constant v. Advanced Micro-Devices, Inc., 848 F.2d 1560, 1571 (Fed. Cir. 1988));
see also Phillips, 415 F.3d at 1323. “[I]t is improper to read limitations from a preferred
embodiment described in the specification—even if it is the only embodiment—into the claims
absent a clear indication in the intrinsic record that the patentee intended the claims to be so
limited.” Liebel-Flarsheim Co. v. Medrad, Inc., 358 F.3d 898, 913 (Fed. Cir. 2004).
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 7 of 39 PageID #:
<pageID>

Page 8 of 39
The prosecution history is another tool to supply the proper context for claim construction
because, like the specification, the prosecution history provides evidence of how the U.S. Patent
and Trademark Office (“PTO”) and the inventor understood the patent. Phillips, 415 F.3d at 1317.
However, “because the prosecution history represents an ongoing negotiation between the PTO
and the applicant, rather than the final product of that negotiation, it often lacks the clarity of the
specification and thus is less useful for claim construction purposes.” Id. at 1318; see also Athletic
Alts., Inc. v. Prince Mfg., 73 F.3d 1573, 1580 (Fed. Cir. 1996) (ambiguous prosecution history
may be “unhelpful as an interpretive resource”).
Although extrinsic evidence can also be useful, it is “‘less significant than the intrinsic
record in determining the legally operative meaning of claim language.’” Phillips, 415 F.3d at
1317 (quoting C.R. Bard, Inc., 388 F.3d at 862). Technical dictionaries and treatises may help a
court understand the underlying technology and the manner in which one skilled in the art might
use claim terms, but technical dictionaries and treatises may provide definitions that are too broad
or may not be indicative of how the term is used in the patent. Id. at 1318. Similarly, expert
testimony may aid a court in understanding the underlying technology and determining the
particular meaning of a term in the pertinent field, but an expert’s conclusory, unsupported
assertions as to a term’s definition are not helpful to a court. Id. Extrinsic evidence is “less reliable
than the patent and its prosecution history in determining how to read claim terms.” Id. The
Supreme Court has explained the role of extrinsic evidence in claim construction:
In some cases, however, the district court will need to look beyond the patent’s
intrinsic evidence and to consult extrinsic evidence in order to understand, for
example, the background science or the meaning of a term in the relevant art during
the relevant time period. See, e.g., Seymour v. Osborne, 11 Wall. 516, 546 (1871)
(a patent may be “so interspersed with technical terms and terms of art that the
testimony of scientific witnesses is indispensable to a correct understanding of its
meaning”). In cases where those subsidiary facts are in dispute, courts will need to
make subsidiary factual findings about that extrinsic evidence. These are the
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 8 of 39 PageID #:
<pageID>

Page 9 of 39
“evidentiary underpinnings” of claim construction that we discussed in Markman,
and this subsidiary factfinding must be reviewed for clear error on appeal.
Teva Pharm. USA, Inc. v. Sandoz, Inc., 574 U.S. 318, 331–32 (2015).
B. 	Departing from the Ordinary Meaning of a Claim Term
There are “only two exceptions to [the] general rule” that claim terms are construed
according to their plain and ordinary meaning: “1) when a patentee sets out a definition and acts
as his own lexicographer, or 2) when the patentee disavows the full scope of the claim term either
in the specification or during prosecution.”2 Golden Bridge Tech., Inc. v. Apple Inc., 758 F.3d
1362, 1365 (Fed. Cir. 2014) (quoting Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362,
1365 (Fed. Cir. 2012)); see also GE Lighting Sols., LLC v. AgiLight, Inc., 750 F.3d 1304, 1309
(Fed. Cir. 2014) (“[T]he specification and prosecution history only compel departure from the
plain meaning in two instances: lexicography and disavowal.”). The standards for finding
lexicography or disavowal are “exacting.” GE Lighting Sols., 750 F.3d at 1309.
To act as his own lexicographer, the patentee must “clearly set forth a definition of the
disputed claim term,” and “clearly express an intent to define the term.” Id. (quoting Thorner, 669
F.3d at 1365); see also Renishaw, 158 F.3d at 1249. The patentee’s lexicography must appear
“with reasonable clarity, deliberateness, and precision.” Renishaw, 158 F.3d at 1249.
To disavow or disclaim the full scope of a claim term, the patentee’s statements in the
specification or prosecution history must amount to a “clear and unmistakable” surrender. Cordis
Corp. v. Bos. Sci. Corp., 561 F.3d 1319, 1329 (Fed. Cir. 2009); see also Thorner, 669 F.3d at 1366
(“The patentee may demonstrate intent to deviate from the ordinary and accustomed meaning of a
2 Some cases have characterized other principles of claim construction as “exceptions” to the
general rule, such as the statutory requirement that a means-plus-function term is construed to
cover the corresponding structure disclosed in the specification. See, e.g., CCS Fitness, Inc. v.
Brunswick Corp., 288 F.3d 1359, 1367 (Fed. Cir. 2002).
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 9 of 39 PageID #:
<pageID>

Page 10 of 39
claim term by including in the specification expressions of manifest exclusion or restriction,
representing a clear disavowal of claim scope.”). “Where an applicant’s statements are amenable
to multiple reasonable interpretations, they cannot be deemed clear and unmistakable.” 3M
Innovative Props. Co. v. Tredegar Corp., 725 F.3d 1315, 1326 (Fed. Cir. 2013).
III. 	LEVEL OF ORDINARY SKILL IN THE ART
It is well established that patents are interpreted from the perspective of one of ordinary
skill in the art (“POSITA”). See Phillips, 415 F.3d at 1313 (“[T]he ordinary and customary
meaning of a claim term is the meaning that the term would have to a person of ordinary skill in
the art in question at the time of the invention, i.e., as of the effective filing date of the patent
application.”). The Federal Circuit has advised that the “[f]actors that may be considered in
determining the level of skill in the art include: (1) the educational level of the inventors; (2) the
type of problems encountered in the art; (3) prior art solutions to those problems; (4) the rapidity
with which innovations are made; (5) sophistication of the technology; and (6) education level of
active workers in the field.” Env’tl Designs, Ltd. v. Union Oil Co. of California, 713 F.2d 693, 696
(Fed. Cir. 1983). “These factors are not exhaustive but are merely a guide to determining the level
of ordinary skill in the art.” Daiichi Sankyo Co. Ltd. v. Apotex, Inc., 501 F.3d 1254, 1256 (Fed.
Cir. 2007).
For the Asserted Patents, Plaintiff’s expert, Dr. Harris, opines that a POSITA “would have
had (1) a bachelor’s degree in electrical engineering or a related field and approximately two years
of industry or academic experience designing or analyzing integrated circuits, or (2) a master’s
degree or Ph.D. in electrical engineering or an equivalent field, with coursework, thesis,
dissertation work, or research experience in semiconductors and integrated circuits.” (Dkt. No.
159-9 at ¶ 10.)
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 10 of 39 PageID #:
<pageID>

Page 11 of 39
For the Hirase Patents, Defendants argue that a POSITA “would have had at least a
Masters’ degree in electrical engineering, physics, chemistry, materials science, or related fields,
and three years of work experience in semiconductor manufacturing.” (Dkt. No. 162 at 9.)
Defendants further 	argue that “[a]dditional graduate education could substitute for work
experience, and additional work experience/training could substitute for formal education.” Id. For
the ’779 Patent, Defendants contend that “[t]he same POSITA definition as the Hirase patents
should apply, except that the required work experience should also include work on the
manufacturing of planar transistors.” Id. at 27.
Having considered the parties’ proposals, and the factors that may be considered in
determining the level of skill in the art, the Court finds a POSITA would have had a bachelor’s
degree in electrical engineering, physics, chemistry, materials science, or related field, and
approximately two years of industry or academic experience designing or analyzing integrated
circuits. Additional education may substitute for industry experience, or vice versa. The Court
notes that any differences in the parties’ proposals do not appear to be significant for the
purpose of claim construction.
IV. 	CONSTRUCTION OF AGREED TERMS
On December 17, 2025, Plaintiff notified the Court via email that it agreed to Defendants’
proposal of plain and ordinary meaning for each of the following claim terms:
Claim Term/Phrase 	Agreed Construction
“substrate”
(’227 Patent: Claim 1; ’764 Patent: Claim 1; ’180
Patent: Claim 1; ’076 Patent: Claim 1)
Plain and ordinary meaning.
“retracted from”
(’076 Patent: Claim 1)
Plain and ordinary meaning.
“made of the second metal film”
(’686 Patent: Claim 29)
Plain and ordinary meaning.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 11 of 39 PageID #:
<pageID>

Page 12 of 39
In view of the parties’ agreement on the proper construction of the identified terms, the Court
hereby ADOPTS the parties’ agreed constructions.
V. 	CONSTRUCTION OF DISPUTED TERMS
The parties dispute the meaning and scope of six terms or phrases in the Asserted Patents.
Each dispute is addressed below.
A. “gate insulating film”
Disputed Term 	Plaintiff’s Proposal 	Defendants’ Proposal
“gate insulating
film”
Plain and Ordinary Meaning. 	“gate insulating film wherein each side
end portion is not in contact with any
overlying insulating sidewall”
1. 	Analysis
The term “gate insulating film” appears in Asserted Claims 1, 2, and 4 of the ’227 Patent;
Asserted Claims 1, 5, 6, 11, 12, 13, 16, 17, 18, and 19 of the ’764 Patent; Asserted Claims 1, 5, 6,
11, 13, 16, 17, 18, 19, 21, and 22 of the ’180 Patent; and Asserted Claims 1, 3, 6, 7, 10, 11, 12,
and 13 of the ’076 Patent. The Court finds that the term is used consistently in the claims and is
intended to have the same general meaning in each claim. The parties dispute whether the term
“gate insulating film” requires construction. Defendants argue that their construction “aligns with
the intrinsic evidence by (1) capturing the ‘present invention’ presented as the alleged solution to
the disparaged prior art’s problem, (2) reflecting the specification’s definition explicitly or by
implication, and (3) being supported, as an independent basis, by the Hirase Patents’ unequivocal
disavowal.” (Dkt. No. 162 at 9-10.)
The Court finds that Defendants’ limitation misrepresents the scope of “the present
invention,” and they fail to show any express or implied definition or unequivocal disavowal. The
specification states that Figures 16A and 16B depict the prior art. (’076 Patent at 5:53–54.) These
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 12 of 39 PageID #:
<pageID>

Page 13 of 39
figures discloses a gate insulating film 104 (yellow), gate electrode 105 (orange), insulating
sidewalls 107 (green), and offset sidewalls 106 (blue).
(Id. at 1:35–60, Figures 16A-B (color added).) The gate insulating film 104’s side ends are
coextensive with the side edge of gate electrode 105 (orange), as indicated by the added red circles
in Figures 16A-B. Defendants argue that this is the cause of the problem that the invention was
designed to solve. Specifically, a “reduction in the dielectric constant and insulation property of
the high dielectric constant gate insulating film is caused at gate electrode end part, so that device
characteristics of the MISFET are deteriorated and the reliability of the gate insulating film is
degraded,” because the side ends of the gate insulating film are coextensive with the side edge of
the gate electrode. (Id. at 2:4–8.)
The specification states that it is “an object of the present invention to improve
characteristics of a MISFET without degrading of a high dielectric constant gate insulating film.”
(Id. at 2:9–12.) The specification then sets out “the present invention” as follows:
Specifically, a semiconductor device according to the present
invention includes: a high dielectric constant gate insulating film
formed on an active region in a substrate; a gate electrode formed
on the high dielectric constant gate insulating film; and an insulating
sidewall formed on each side surface of the gate electrode. . . . [T]he
high dielectric constant gate insulating film is continuously formed
so as to extend from under the gate electrode to under the insulating
sidewall, and at least part of the high dielectric constant gate
insulating film located under the insulating sidewall has a smaller
thickness than a thickness of part of the high dielectric constant gate
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 13 of 39 PageID #:
<pageID>

Page 14 of 39
insulating film located under the gate electrode.
(Id. at 2:47–59 (emphasis added).) Thus, the “present invention” solves the problem of the gate
insulating film deteriorating at the gate electrode edge by continuously forming the gate insulating
film so it extends from under the gate electrode to under the insulating sidewall. Example of this
configuration are illustrated in Figures 1 and 2.
(Id. at Figures 1and 2 (color added).) The red circles show that the gate insulating film (yellow)
extends from under the gate electrode (orange) to under the insulating sidewall (green in Figure 1,
blue in Figure 2). More importantly, the claim language of the ’227, ’764, ’180, and ’076 Patents
capture this limitation. For example, Claim 1 of the ’227, ’764, and ’180 Patents recite that “the
high dielectric constant gate insulating film is continuously formed so as to extend from under the
gate electrode to under the [first] insulating sidewall.” (’227 Patent at 21:49–51; ’764 Patent at
21:43–45; ’180 Patent at 21:16–18.) Similarly, Claim 1 of the ’076 Patent recites “a width of the
gate insulating film along a gate length is larger than a width of the gate electrode along the gate
length,” and “an end of the gate insulating film under the insulating sidewall.” (’076 Patent at
22:1–5.) Thus, the claim language leaves no ambiguity as to the requirement 	of the “gate
insulating film.”
Regarding Defendants’ construction, the Court first notes that the construction repeats the
disputed term “gate insulating film,” and then adds fourteen words to it. For the reasons discussed
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 14 of 39 PageID #:
<pageID>

Page 15 of 39
below, these fourteen additional words would improperly limit the meaning of “gate insulating
film.” First, the claims could have specified this narrower meaning of gate insulating film if that
is what the patentees intended. For example, a dependent claim expressly requires non-contact
with an insulating sidewall, which indicates that independent Claim 1’s “gate insulating film” is
not so limited. Specifically, dependent Claim 21 of the ’764 Patent recites “[t]he semiconductor
device of claim 1, wherein each side end portion of the high dielectric constant gate insulating
film is not in contact with the first insulating sidewall.” (’764 Patent at 22:56–58 (emphasis
added).) None of the independent claims across the four patents expressly recites a “not in contact”
requirement like the one in Claim 21. Liebel-Flarsheim, 358 F.3d at 910 (“[W]here the limitation
that is sought to be ‘read into’ an independent claim already appears in a dependent claim, the
doctrine of claim differentiation is as its strongest.” (citation omitted).) The presence of this
limitation in a dependent claim indicates that the corresponding independent claim is broader, and
that “gate insulating film” should not be construed as Defendants suggest.
Defendants first argue that the patents openly disparage the prior art’s contact between the
side ends of the gate insulating film and the adjoining sidewalls. (Dkt. No. 162 at 11 (citing ’076
Patent at 1:67–2:8).) Defendants contend that “the present invention” solves this problem by
“prevent[ing] end portions of the high dielectric constant gate insulating film from being in contact
with the sidewalls.” (Dkt. No. 162 at 11 (citing ’076 Patent at 2:9–19, 4:42–51) (emphasis in
original).)
The Court notes that both portions of the specification that Defendants cite teach that in
the “present invention” the gate insulating film is under the sidewalls. This is what is universally
different from the prior art, and what is recited in the claims. See, e.g., ’764 Patent at 2:10–14 (“To
achieve the above-described object, the inventors of the present application have devised a
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 15 of 39 PageID #:
<pageID>

Page 16 of 39
MISFET structure in which a high dielectric constant gate insulating film is kept remaining under
sidewalls …”); 4:39-41 (“According to the present invention, a high dielectric constant gate
insulating film is continuously formed so as to extend from under a gate electrode to under a
sidewall.”). Thus, the summary of “the present invention” does not restrict the shape or position
of the ends of the gate insulating film, and none of the descriptions of “the present invention” in
the specification imposes the limitation Defendants seek. Accordingly, Defendants’ reliance on
Verizon Servs. Corp. v. Vonage Holdings Corp., 503 F.3d 1295 (Fed. Cir. 2007), and VirnetX, Inc.
v. Cisco Sys., Inc., 767 F.3d 1308 (Fed. Cir. 2014) is misplaced.
Second, the term “side end portions” is not defined in the specification. Indeed, the
remaining figures in the patent may be understood to have more than two “side end portions.” For
example, Figure 5 could show six potential “side end portions,” two of which are in contact with
offset sidewall 6 (annotated 1A & 1B) and two of which are in contact with insulating sidewall 7
(annotated 2A & 2B).
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 16 of 39 PageID #:
<pageID>

Page 17 of 39
(’076 Patent at Figure 5 (annotated.) Likewise, Figure 2 could show four potential “side end
portions,” two of which are in contact with offset sidewall 6 (annotated 1A & 1B) and two of
which are in contact with insulating sidewall 7 (annotated 2A & 2B).
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 17 of 39 PageID #:
<pageID>

Page 18 of 39
(’076 Patent at Figure 5 (annotated).) Defendants’ construction also introduces the term
“overlying,” which does not appear in the specification. If Defendants’ construction was indeed
the “present invention,” the Court would expect to find the term included in the specification. This
indicates that “overlying” is not required by the claims or the specification, but instead would
improperly redraft the claim language.
Defendants 	also 	argue 	that 	all 	embodiments 	consistently 	implement 	“the 	present
invention” to solve the prior art’s problem by avoiding contact between the gate insulating film’s
side ends and the overlying sidewalls. (Dkt. No. 162 at 12 (citing ’076 Patent at Figures 1-15D).)
Defendants contend that in Figure 1, the specification teaches that “each side end portion of the
high dielectric constant gate insulating film 4A is not in contact with the sidewall 7[,]” with the
added red circles showing no contact between the gate insulating film’s (yellow) side ends and
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 18 of 39 PageID #:
<pageID>

Page 19 of 39
overlying sidewall 7 (green).
(Dkt. No. 162 at 12 (citing ’076 Patent at 6:32–34, Figure 1 (colors added) (emphasis added)).)
Defendants further argue that the specification teaches that in Figure 2 “each side end portion of
the high dielectric constant gate insulating film 4B is not in contact with the offset sidewall 6,” to
achieve the same benefits.
(Dkt. No. 162 at 12-13 (citing ’076 Patent at 7:65–8:7, Figure 2 (colors added) (emphasis added)).)
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 19 of 39 PageID #:
<pageID>

Page 20 of 39
According to Defendants, the specification repeats the same teaching of Figures 1 and 2 for the
embodiments depicted in Figures 3 to 5, with only the gate insulating film’s numeral and overlying
sidewall being different. (Dkt. No. 162 at 13 (citing ’076 Patent at 9:7–20, Figure 3, 9:62–10:9,
Figure 4, 11:3–16, Figure 5).) Defendants argue that all disclosed embodiments and their figures
“repeatedly and consistently” characterize the gate insulating film as having side ends which do
not contact either the overlying sidewall 7 or the overlying offset sidewall 6. (Dkt. No. 162 at 13-
14 (citing Figures 1, 3-6, 8-11, 13, 2, 7, 12, 14, 15).)
As discussed above, the “present invention” solves the problem of the gate insulating film
deteriorating at the gate electrode edge by continuously forming the gate insulating film so it
extends from under the gate electrode to under the insulating sidewall. For the embodiment
identified by Defendants, the specification states that it is the existence of the high dielectric
constant gate insulating film under the sidewall that makes capacitive coupling between the gate
electrode and the n-type extension region stronger in the vicinity of the end portion of the gate
electrode. See, e.g., ’076 Patent at 6:42–46, 8:13–17. Again, the claim language of the ’227, ’764,
’180, and ’076 Patents capture this limitation.
Moreover, while certain embodiments identify a “gate insulating film” whose side end
portions are not in contact with a sidewall, the specification also includes embodiments where the
side end portions of the gate insulating film are in contact with a sidewall, See, e.g., ’076 Patent
at Figure 2 (disclosing embodiment where gate insulating film 4B is in contact with sidewall 7).
Simply stated, the “gate insulating film” claim language is broader than the preferred embodiments
that Defendants rely upon. “The Federal Circuit has consistently held that ‘particular embodiments
appearing in the written description will not be used to limit claim language that has broader
effect.’” Weatherford Tech. Holdings, LLC v. Tesco Corp., No. 2:17-CV-456, 2018 U.S. Dist.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 20 of 39 PageID #:
<pageID>

Page 21 of 39
LEXIS 110507, at *33 (E.D. Tex. July 2, 2018) (quoting Innova/Pure Water, Inc. v. Safari Water
Filtration Sys., Inc., 381 F.3d 1111, 1117 (Fed. Cir. 2004)).
Thus, the Court rejects Defendants’ attempt to improperly narrow the ordinary meaning of
the term “gate insulating film.” Effective Expl,. LLC v. Bluestone Nat. Res. II, LLC, No. 2:16-CV-
00607-JRG-RSP, 2017 U.S. Dist. LEXIS 118002, at *39 (E.D. Tex. July 27, 2017) (rejecting
proposed construction that “simply uses the exact language of the claim,” but tries to “add[]”
narrowing limitations to it). Finally, the Court finds that there is no “clear and unequivocal”
disavowal sufficient to justify Defendants’ construction. Poly-Am., L.P. v. API Indus., Inc., 839
F.3d 1131, 1136 (Fed. Cir. 2016). For these reasons, the Court rejects Defendants’ addition of
limitations not found in the claim language, and gives the term its plain and ordinary meaning.
2. 	Court’s Construction
For the reasons set forth above, the term “gate insulating film” is given its plain and
ordinary meaning.
B. “outer end of the insulating sidewall”
Disputed Term 	Plaintiff’s Proposal 	Defendants’ Proposal
“outer end of the
insulating sidewall”
“outer end of the outermost
sidewall component that is directly
on the gate insulating film”
“outer end of the outermost
sidewall layer that is directly on
the top surface of the gate
insulating film”
1. 	Analysis
The term “outer end of the insulating sidewall” appears in Asserted Claims 1 of the ’180
Patent, and Asserted Claim 1 of the ’076 Patent. The Court finds that the term is used consistently
in the claims and is intended to have the same general meaning in each claim. The parties agree
the outermost sidewall must be “directly on” the gate insulating film. (Dkt. No. 159 at 13-14.)
Plaintiff also states it “does not understand there to be a meaningful distinction between
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 21 of 39 PageID #:
<pageID>

Page 22 of 39
‘component’ and ‘layer’ for the construction of this claim term.” (Dkt. No. 164 at 10 n. 8.) Thus,
there is not a dispute for this aspect of the construction. The only dispute is whether the outermost
sidewall should be directly on a “the top surface” of the gate insulating film, as Defendants
contend.
Defendants argue that in every embodiment of the ʼ076 and ʼ180 Patents, the outermost
sidewall rests on the top surface of the gate insulating film. (Dkt. No. 162 at 19 (citing ʼ076 Patent
at Figures 1-15D).) Defendants contend that the specification never disclose any other embodiment
where the outermost sidewall is directly on a surface of the gate insulating film other than the top
surface of the gate insulating film. (Dkt. No. 162 at 19.) Defendants further contend that Plaintiff’s
own statements in its Inter partes review Patent Owner Preliminary Responses (“IPR POPRs”)
about the outermost sidewalls in the patents’ Figures 7 and 8 compel the inclusion of “top surface.”
Id.
Plaintiff responds that there is no intrinsic or extrinsic support for the “top surface”
limitation Defendants seek to impose. (Dkt. No. 164 at 9.) Plaintiff argues that “top surface” is not
a term used in these patents, and to the extent the gate insulating film can be understood to have a
single “top surface,” all the figures depict that “top surface” under the gate. (Id. at 9-10.) Regarding
the IPR, Plaintiff contends that in Figure 7, the outermost sidewall component directly on the gate
insulating film is offset sidewall 6 (blue), while in Figure 8, it is insulating sidewall 7 (green).
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 22 of 39 PageID #:
<pageID>

Page 23 of 39
(Id. at 10 (citing Figures 7–8 reproduced from Dkt. No. 162 at 20).) Plaintiff argues that this is a
function of “directly on,” which all parties agree is a necessary part of this claim term. (Dkt. No.
164 at 10.)
The Court notes that the surrounding language in Claim 1 of the ’180 Patent recites that
“an end of the high dielectric constant gate insulating film under the insulating sidewall is located
at a predetermined distance from an outer end of the insulating sidewall toward the gate
electrode.” (’180 Patent at 21:19–22 (emphasis added).) The Court notes that the only discussion
of “predetermined distance” in the specification appears in the following context:
In each of the first through eighth embodiments, a shape of each side
surface of the high dielectric constant gate insulating film 4 in which
the notch 20 is provided in the part located under each side end
portion of the sidewall 7 or the offset sidewall 6 is not limited to a
semicircular shape shown in FIG. 6, 7, 8 or 10. For example, each
side surface of the high dielectric constant gate insulating film 4 may
be a perpendicular plane to the substrate surface. That is, a side
surface of the high dielectric constant gate insulating film 4 may be
located at a predetermined distance from a side end surface of the
sidewall 7 or the offset sidewall 6 toward the gate electrode 5.
(’180 Patent at 20:63–21:7, Figure 6 (emphasis added).) Plaintiff argues that this describes tapered,
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 23 of 39 PageID #:
<pageID>

Page 24 of 39
notched, and otherwise non-planar edges to the gate insulating film “under the insulating sidewall.”
(Dkt. No. 159 at 14.) According to Plaintiff, nothing in the patents or prosecution history limits
the “outer end of the insulating sidewall” to a sidewall component that sits directly on a flat “top
surface” of a gate insulating film. Id. The Court agrees that Defendants’ construction introduces
unwarranted ambiguity given this disclosure.
2. 	Court’s Construction
For the reasons set forth above, the Court construes the term “outer end of the insulating
sidewall” to mean “outer end of the outermost sidewall layer that is directly on the gate
insulating film.”
C. “offset sidewall”
Disputed Term 	Plaintiff’s Proposal 	UMC’s Proposal3
“offset sidewall” 	Plain and Ordinary Meaning. 	“a sidewall adjacent a side of the gate
electrode and spaced from the substrate”
1. 	Analysis
The term “offset sidewall” appears in Asserted Claim 4 of the ’764 Patent. The parties
dispute whether the term “offset sidewall” requires construction. Plaintiff argues that UMC’s
construction includes two limitations that do not appear in the claims or specification. (Dkt. No.
159 at 17.) Plaintiff further argues that UMC’s construction introduces needless ambiguity and
redundancy. Id. Plaintiff contends that UMC’s construction does nothing to define “sidewall,”
which appears in both the claim term and UMC’s construction. Id. According to Plaintiff, the claim
language already states that the offset sidewall in Claim 4 is “formed on each side surface of” the
gate electrode. Id. Plaintiff further argues that there is no support for redundantly requiring an
3 For the sole purpose of this case and this Patent, TSMC states that it takes no position on this
term or its construction.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 24 of 39 PageID #:
<pageID>

Page 25 of 39
offset sidewall to both be “formed on” each side surface of the gate electrode and a “adjacent a
side of” that gate electrode. (Id. at 18.)
Regarding the second part of UMC’s construction, Plaintiff contends that defining “offset”
as “spaced from the substrate” would add a limitation not grounded in the claim language or the
specification. Id. Plaintiff argues that the phrase “spaced from” is not used in the Patent. Id.
Plaintiff further argues that UMC uses “spaced from” to refer to a vertical distance between the
offset sidewall and the substrate beneath it. Id. Plaintiff contends that this additional limitation on
the meaning of “offset sidewall” contradicts the plain and ordinary meaning a POSITA would
afford the term. (Id. (citing Dkt. No. 159-9 at ¶ 31).)
Plaintiff also argues that the specification consistently describes an offset sidewall as the
inner spacer formed on each side surface of the gate electrode and interposed laterally between the
gate electrode and an outer sidewall. (Dkt. No. 159 at 18 (citing ’764 Patent at 1:52–55, 7:37–39,
10:36–38, 15:39–42, 17:29–31, 19:16–18, 15:55–59, 17:47–50, 19:33–37).) Plaintiff contends that
none of these disclosures addresses how the offset sidewall is positioned vertically relative to the
“substrate.” (Dkt. No. 159 at 19.) According to Plaintiff, the “offset” is defined based on its
horizontal position relative to the gate electrode and an outer sidewall. Id.
UMC argues that Plaintiff’s expert, Dr. Harris, admitted that the “offset sidewall” term
requires construction. (Dkt. No. 162 at 23 (citing Dkt. No. 162-2 at 225:23-226:8).) UMC further
argues that a construction is required to avoid speculation as to the “offset sidewall” term’s
meaning. (Dkt. No. 162 at 23.) UMC contends that its construction is correct in view of the ’784
Patent disclosure. (Id. at 24 (citing ’764 Patent at 15:27–42).) UMC also argues that only one
structure for the offset sidewall (i.e., adjacent a side of the gate electrode and spaced from the
substrate) is consistently described. (Id. at 24 (citing ’764 Patent at 7:30–8:11, 8:35–40, 8:55–9:14,
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 25 of 39 PageID #:
<pageID>

Page 26 of 39
9:36–10:2, 10:29–11:32, 13:25–14:62, 15:24–16:53, 17:13–18:30, 18:61–19:45, 19:56–20:56,
21:9–10, Figures 2-5, 7-8, 12E-G, 13E-G, 14E-G, 15A-D).) UMC contends that the specification
only describes the offset sidewall as being separated from the substrate by a gate insulating film.
(Dkt. No. 162 at 25.)
Finally, UMC argues that for the claimed semiconductor device to achieve its asserted
advantage, the offset sidewall must be adjacent a side of the gate electrode and spaced from the
substrate. (Dkt. No. 162 at 25 (citing ’764 Patent at 8:3–7).) UMC contends that its construction
makes clear that the offset sidewall is spaced from the substrate (i.e., at least by the high dielectric
constant gate insulating film that is under the offset sidewall), which is required to achieve the
purported advantage of the invention. (Dkt. No. 162 at 25.)
Starting with the claim language, the Court notes that Claim 4 of the ’764 Patent recites
“the semiconductor device of Claim 1, wherein the first insulating sidewall is an offset sidewall.”
’764 Patent at 21:56–57. Claim 1 recites “a first insulating sidewall formed on each side surface
of the gate electrode.” Id. at 21:38–39. The Court agrees with Plaintiff that the claim language
already states that the offset sidewall in Claim 4 is “formed on each side surface of” the gate
electrode. UMC’s construction restates that requirement, defining the offset sidewall as “adjacent
a side of the gate electrode.” Accordingly, the Court rejects this redundant construction. O2 Micro
Int'l Ltd. v. Beyond Innovation Tech. Co., 521 F.3d 1351, 1362 (Fed. Cir. 2008) (“Claim
construction ‘is not an obligatory exercise in redundancy.’”) (quoting U.S. Surgical Corp. v.
Ethicon, Inc., 103 F.3d 1554, 1568 (Fed. Cir. 1997)).
Regarding the second part of UMC’s construction, Claim 1 further recites that “the high
dielectric constant gate insulating film is continuously formed so as to extend from under the gate
electrode to under the first insulating sidewall.” (’764 Patent at 21:43–45.) Thus, the consistent
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 26 of 39 PageID #:
<pageID>

Page 27 of 39
description of the offset sidewall structure and method of forming that structure is captured in the
claim language. As UMC argues, the specification explains that “the existence of the high
dielectric constant gate insulating film 4B under the offset sidewall 6 makes capacitive coupling
between the gate electrode and the n-type extension region 10 stronger in the vicinity of the end
portion of the gate electrode 5.” (Dkt. No. 162 at 25 (citing ’764 Patent at 8:3–7).) This is recited
in the claims, and UMC’s construction would introduce unwarranted ambiguity into the claim
language.
2. 	Court’s Construction
For the reasons set forth above, the term “offset sidewall” is given its plain and ordinary
meaning.
D. “sidewall spacer”
Disputed Term 	Plaintiff’s Proposal 	UMC’s Proposal4
“sidewall spacer” 	Plain and Ordinary Meaning. 	“a sidewall spacer that is not on top of
any portion of the gate electrode”
1. 	Analysis
The term “sidewall spacer” appears in Asserted Claim 2 of the ’779 Patent. The parties
dispute whether the term “sidewall spacer” requires construction. Dependent Claim 2 recites the
following:
2. The semiconductor device of claim 1, wherein
the first gate electrode includes first sidewall spacers formed on side
surfaces 	thereof 	and 	first 	insulating 	spacers 	interposed
between the first gate electrode and the first sidewall spacers,
the second gate electrode includes second sidewall spacers formed
on 	side 	surfaces 	thereof 	and 	second 	insulating 	spacers
interposed between the second gate electrode and the second
sidewall spacers, and
the first insulating spacers are thinner than the second insulating
4 For the sole purpose of this case and this Patent, TSMC states that it takes no position on this
term or its construction.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 27 of 39 PageID #:
<pageID>

Page 28 of 39
spacers.
(’779 Patent at 14:23–33.) The specification provides a preferred embodiment illustrating how
insulating film 8 (e.g., silicon nitride film) is formed on the entire surface of the semiconductor
substrate 50, as illustrated in Figure 3.
(Id. at 9:7–11, Figure 3 (partial) (highlight added).) The specification further states a resist pattern
11 covers the second pMIS transistor region and the insulting film 8 is subjected to dry etched as
shown in Figure 5.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 28 of 39 PageID #:
<pageID>

Page 29 of 39
(Id. at 9:44–53, Figure 5 (partial) (highlight added).) The specification discloses that the offset
spacer 8a has a thickness that “is smaller than the original thickness (e.g., about 6 nm) of the
insulating film 8.” (Id. at 9:53–55.) The specification states that after the resist pattern 11 is
removed “the semiconductor substrate 50 is subjected to an oxidation treatment in, for example,
plasma composed of a gas containing oxygen and at, for example, about 400° C.” (Id. at 9:56–59.)
This results in “the thickness of the interface layer 2a of the gate insulating film 52a in the first
pMlS transistor region increases, from both sides thereof, by about 0.3 nm,” as shown in Figure 6.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 29 of 39 PageID #:
<pageID>

Page 30 of 39
(Id. at 9:56–61, Figure 6 (partial) (highlight added).) The specification further discloses that “a
silicon dioxide film 13a with a thickness of about 0.3 nm is formed on the upper surface and the
side surfaces of the silicon film 7a of the gate electrode 53a located in the first pMIS transistor
region.” (Id. at 10:6–9.) “A silicon dioxide film and a silicon nitride film are sequentially deposited
on the entire surface of the semiconductor substrate 50, and then, the deposited silicon nitride film
and the deposited silicon dioxide film are etched back.” (Id. at 11:11–14.) As shown in Figure 8,
sidewall spacers l8a and 18b are formed on both sides of the gate electrodes 53a and 53b.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 30 of 39 PageID #:
<pageID>

Page 31 of 39
(Id. at 11:14–17, Figure 8 (partial) (highlight added).) The specification states that each of the
sidewall spacers 18a and 18b includes an inner sidewall spacer 16a and 16b of a silicon dioxide
film with an L-shaped cross section and an outer sidewall spacer 17a and 17b of a silicon nitride
film formed on the inner sidewall spacer 16a and 16b. (Id. at 11:17–21.) The specification further
discloses that “the silicon dioxide film 13a present on the upper face of the gate electrode 53a and
on the active region 50a and the silicon dioxide film 13c present on the upper face of the gate
electrode 53c and on the active region 50c are also etched back.” (Id. at 11:49–53.) As illustrated
in Figure 8, “the offset spacers 8a and the remaining silicon dioxide film 13a are interposed
between the side surfaces of the gate electrode 53a and the sidewall spacers 18a, and the remaining
silicon dioxide film 13a is also interposed between the active region 50a (the p-type extension
regions 9a) and the sidewall spacers 18a” (Id. at 11:53–59.)
The specification states that in the final step a metal film (e.g., Nickel) is deposited on the
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 31 of 39 PageID #:
<pageID>

Page 32 of 39
entire surface of the semiconductor and annealing is performed. (Id. at 12:37–38.) The
specification discloses that “[t]he surface portions of the silicon films 7a, 7b, 7c, and 7c of the gate
electrodes 53a, 53b, 53c, and 53d, the surface portions of the p-type source/drain regions 19a and
19b, and the surface portions of the n-type source/drain regions 19c and 19d are caused to react
with the deposited metal film to form metal silicide layers 20a, 20b, 20c, and 20d,” as shown in
Figure 9.
(Id. at 12:38–44, Figure 9 (partial) (highlight added).) Given this background, the Court agrees
that UMC’s construction is incorrect and would be unhelpful to the factfinder, because it does not
define “sidewall” or “spacer.” UMC’s construction restates those terms and then adds thirteen
additional words. Moreover, UMC’s negative limitation (i.e., “not on top of any portion of the gate
electrode”) is not required by the intrinsic record. For a negative limitation to be read into claim,
it must be supported by either “the words of the claim” or an “express disclaimer or independent
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 32 of 39 PageID #:
<pageID>

Page 33 of 39
lexicography in the written description that would justify adding that negative limitation.” Omega
Eng’g, Inc. v. Raytek Corp., 334 F.3d 1314, 1323 (Fed. Cir. 2003).
As discussed above, nothing in the Patent’s claims or written description departs from the
plain and ordinary meaning of a “sidewall spacer.” The claim language is consistent with the plain
meaning of the term. Furthermore, the specification similarly treats “sidewall spacers” as
insulators flanking the sides of the gate electrode in describing both the prior art and the present
invention. (See, e.g., ’779 Patent at 2:43–48, 4:38–46, 11:14–32.) Thus, the intrinsic evidence does
not redefine “sidewall spacer” to impose a categorical limitation forbidding any portion of a
sidewall spacer from being “on top of” any portion of the gate electrode.
UMC argues that in all disclosed embodiments, the sidewall spacers are formed via
sequential deposition of a silicon dioxide film and a silicon nitride film over the entire surface of
the semiconductor substrate and then etched back. (Dkt. No. 162 at 28 (citing ’779 Patent at 11:11–
17).) UMC further argues that as a result of etching, no silicon dioxide film (or silicon nitride film
previously deposited on top of the silicon dioxide film) remains on top of any portion of the gate
electrode. (Dkt. No. 162 at 28 (citing ’779 Patent at 11:49–53).) UMC contends that this is the
only arrangement disclosed in the ’779 Patent, because a film would not serve to electrically isolate
the gate from the source and drain contacts in that location. (Dkt. No. 162 at 28) (citing ’779 Patent
at 2:39–57, 4:38–63, 11:11–12:35, Figures 1-9).) According to UMC, the sidewall spacers are
inherently adjacent to the side of the gate electrode, because the claim language requires that they
are “formed on side surfaces” of the first and second gate electrodes, respectively. (Dkt. No. 162
at 29.)
As UMC concedes, the claim language itself requires the sidewall spacers to be “formed
on side surfaces” of the first and second gate electrodes. However, neither the claim language nor
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 33 of 39 PageID #:
<pageID>

Page 34 of 39
the specification further limit the “sidewall spacers.” Instead, the specification discloses a
preferred embodiment where silicon dioxide film or silicon nitride film previously deposited on
top of the silicon dioxide film is removed. However, this is just the preferred embodiment and
does not justify the negative limitation UMC urges. As Plaintiff argues, a POSITA would
understand “sidewall spacer” to mean “a dielectric intended to electrically isolate a gate from a
contact … adjacent to a side of the gate electrode.” (Dkt. No. 164 at 13 (citing Dkt. No. 159-9 at
¶¶ 35–36).) The Court agrees and finds that UMC’s additional limitation is improper and should
not be read into the claims.
2. 	Court’s Construction
For the reasons set forth above, the term “sidewall spacer” is given its plain and ordinary
meaning.
E. “[first] insulating spacers interposed between the [first] gate electrode
and the [first] sidewall spacers”
Disputed Term 	Plaintiff’s Proposal 	UMC’s Proposal5
“[first] insulating
spacers interposed
between the [first] gate
electrode and the [first]
sidewall spacers”
Plain and Ordinary Meaning. 	“insulating spacers in contact with a
side surface of the gate electrode
between the gate electrode and the
sidewall spacers”
1. 	Analysis
The phrase “[first] insulating spacers interposed between the [first] gate electrode and the
[first] sidewall spacers” appears in Asserted Claim 2 of the ’779 Patent. The parties dispute
whether the phrase “[first] insulating spacers interposed between the [first] gate electrode and the
[first] sidewall spacers” requires construction. Dependent Claim 2 recites the following:
2. The semiconductor device of claim 1, wherein
5 For the sole purpose of this case and this Patent, TSMC states that it takes no position on this
term or its construction.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 34 of 39 PageID #:
<pageID>

Page 35 of 39
the first gate electrode includes first sidewall spacers formed on side
surfaces 	thereof 	and 	first 	insulating 	spacers 	interposed
between the first gate electrode and the first sidewall spacers,
the second gate electrode includes second sidewall spacers formed
on 	side 	surfaces 	thereof 	and 	second 	insulating 	spacers
interposed between the second gate electrode and the second
sidewall spacers, and
the first insulating spacers are thinner than the second insulating
spacers.
(’779 Patent at 14:23–33 (emphasis added).) Claim 2 requires that the insulating spacer be
“interposed between” the gate electrode and the sidewall spacer. The Collins Dictionary 10th ed.
2009 defines “interpose” as “to put or place between or among other things.” (Dkt. No. 159-23 at
4.) Thus, the claim language means what it says. The insulating spacer must be placed between
those structures.
UMC’s construction does not define “interposed” or any other claim term, but instead adds
an unclaimed requirement that the insulating spacers be “in contact with a side surface of the gate
electrode.” The natural and customary meaning of “interposed between” is placed between, and
not “in contact with.” The plain language of the claim does not require the first or second insulating
spacers to be in contact with a side surface of the gate electrode, and the specification has no
applicable lexicography or clear disavowal to rewrite this claim term. Moreover, wherever the’779
Patent requires particular structures to be in contact with others, the claims and specification
expressly state those requirements. (See, e.g., ’779 Patent at Claim 1 (“a first interface layer being
in contact with the semiconductor substrate … a second interface layer being in contact with the
semiconductor substrate” (emphasis added)); Claim 4 (“the second silicon film is in contact with
the second insulating spacers”) (emphasis added)); 4:4–23; 11:42–45.)
UMC argues that term should be construed to require the insulating spacers contact a side
surface of the gate electrode between the gate electrode and the sidewall spacers to resolve the
inherent ambiguity. (Dkt. No. 162 at 30.) As discussed above, UMC contends that the initial
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 35 of 39 PageID #:
<pageID>

Page 36 of 39
deposition of the film (e.g., a silicon nitride film) that forms the first and second insulating spacers
covers the first and second gate electrodes. (Id. at 30 (citing ’779 Patent at 6:13–15, 9:7–11).)
According to UMC, “there is no teaching or support in the ’779 patent for an insulating spacer that
is not in contact with a side surface of the gate electrode nor is there any embodiment in which
any structure other than an insulating spacer is between a gate electrode and a sidewall spacer.”
(Dkt. No. 162 at 30-3 (citing ’779 Patent at 2:4–15, 4:38–5:3, 5:43–61, 6:5–27, 8:43–60, 9:7–11,
9:44–55, 10:6–25, 11:49–64, Figures 1-9).). UMC further argues that the oxidation teachings of
the ’779 Patent also require contact by the insulating spacers with a side surface of the gate
electrode. (Dkt. No. 162 at 31(citing ’779 Patent at Figure 6, 10:26–32).)
The Court agrees that the preferred embodiment discloses an insulating spacer that in
contact with a side surface of the gate electrode. However, the claims are not limited to the
preferred embodiment. Moreover, this claim term is equally understandable to a POSITA and a
layperson alike. While the insulating spacers can touch the gate electrode, nothing in the claim
language requires it, and UMC points to no “express disclaimer or independent lexicography”
justifying its proposed additional limitation. Omega Eng’g, 334 F.3d at 1323.
2. 	Court’s Construction
For the reasons set forth above, the phrase “[first] insulating spacers interposed between
the [first] gate electrode and the [first] sidewall spacers” is given its plain and ordinary
meaning.
F. 	“effective work function”
Disputed Term 	Plaintiff’s Proposal 	Defendants’ Proposal
“effective work
function”
“a work function obtained
from electrical characteristics
of a MIS transistor”
Plain and ordinary meaning; no
construction necessary
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 36 of 39 PageID #:
<pageID>

Page 37 of 39
1. 	Analysis
The term “effective work function” appears in Asserted Claim 15 of the ’779 Patent. The
parties dispute whether the term “effective work function” requires construction. Plaintiff argues
that the “Summary” section of the specification defines “effective work function” as follows:
Note that the “effective work function” is a work function obtained
from electrical characteristics of a MIS transistor. Specifically, the
effective work function is obtained by incorporating influence such
as a level in an insulating film into a work function related to
physical properties and representing a difference between a vacuum
level and an energy level of a metal.
(Dkt. No. 159 at 25 (citing ’779 Patent at 3:17–23).) Plaintiff contends that this is a “strong
indicator of lexicography,” because “quotation marks are a strong indicator that what follows is a
definition” of that term. (Dkt. No. 159 at 25 (citing Seagen Inc. v. Daiichi Sankyo Co., Ltd., 2021
WL 4168660 (E.D. Tex. Sept. 14, 2021).) According to Plaintiff, the specification unambiguously
defines what an “effective work function is.” (Dkt. No. 164 at 14 (emphasis in original).)
The Court disagrees with Plaintiff’s analysis. “[T]he standard for lexicography is
exacting,” Baxalta Inc. v. Genentech, Inc., 972 F.3d 1341, 1349 (Fed. Cir. 2020), and requires
“‘clearly set[ting] forth a definition of the disputed claim term’ other than its plain and ordinary
meaning[,]” Thorner, 669 F.3d at 1365 (citation omitted). That standard is not met here. The
purported definition does not define what effective work function (“EWF”) is, but instead
addresses how to obtain EWF. The words “obtained from electrical characteristics” in the
proposed construction would be understood by a POSITA as referring to how to obtain an EWF
value through a laboratory experiment. Indeed, the specification expressly teaches that increasing
a layer’s equivalent oxide thickness (“EOT”) (which is a physical characteristic) increases the
EWF. (’779 Patent at 4:29–31 (“[S]ince an EOT of the gate insulating film of the first MIS
transistor increases, an effective work function of the first MIS transistor increases.”), see also id.,
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 37 of 39 PageID #:
<pageID>

Page 38 of 39
5:64–67, 13:23–27 (same).) Accordingly, the Court agrees with Defendants that the cited passage
is a high-level description about obtaining an EWF value and does not define the term.
Moreover, Plaintiff’s expert, Dr. Harris, explained that EWF “has a known meaning in this
art” that he “ha[s] been very familiar with for many years, even before this patent was disclosed.”
(Dkt. No. 162-2 at 156:18–24). Likewise, Dr. Harris does not limit the specification’s definition
to the one line proposed by Plaintiff in his declaration, but instead includes the further qualification
that refers to physical properties and how the effective work function is obtained. (Dkt. No. 159-
9 at ¶ 42 (citing ’779 Patent at 3:17-23).) Again, Plaintiff’s purported definition does not include
the “physical properties” disclosed in the specification. Accordingly, the Court finds that “[t]he
specification here does not clearly indicate the patentee’s intent to give [“effective work function”]
a unique meaning different from its ordinary and customary meaning to one of skill in the art.”
Laryngeal Mask Co. v. Ambu A/S, 618 F.3d 1367, 1372 (Fed. Cir. 2010). Thus, the term is given
its plain and ordinary meaning.
2. 	Court’s Construction
For the reasons set forth above, the term “effective work function” is given its plain and
ordinary meaning.
VI. 	CONCLUSION
The Court adopts the constructions above for the disputed terms of the Asserted Patents.
Furthermore, the parties should ensure that all testimony that relates to the terms addressed in this
Order is constrained by the Court’s reasoning. However, in the presence of the jury the parties
should not expressly or implicitly refer to each other’s claim construction positions and should not
expressly refer to any portion of this Order that is not an actual construction adopted by the Court.
The references to the claim construction process should be limited to informing the jury of the
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 38 of 39 PageID #:
<pageID>

Page 39 of 39
constructions adopted by the Court.
____________________________________
RODNEY GILSTRAP
UNITED STATES DISTRICT JUDGE
So ORDERED and SIGNED this 30th day of January, 2026.
Case 2:24-cv-00730-JRG Document 204 Filed 01/30/26 Page 39 of 39 PageID #:
<pageID>